Analysis of Parallel Hierarchical Matching Schedulers for Input-Queued Switches under Different Traffic Conditions

Input-queued packet switches are more scalable than output-queued ones. However, due to HOL blocking, their throughput is poor. The Virtual Output Queueing (VOQ) switch architecture and several buffer schedulers have been proposed to overcome this problem. Among them, the class of iterative maximal matching algorithms, with a first example being Parallel Iterative Matching (PIM), which uses random selection, and iSLIP that uses round-robin selection, and has become a de facto standard in switching research. iSLIP admits efficient practical implementations, and has several variants with different pointer updating strategies like FIRM, DRRM and RDSRR that improve performance. In previous work, we formulated a new scheduler, Parallel Hierarchical Matching (PHM), which compares favorably to iSLIP-like algorithms. PHM can be considered a parallelization of previous high-performance sequential hierarchical matching algorithms, like 2DRR or WWFA. In this paper we compare their delay performance for the same decision response-time, determined from ASIC implementations, and for different traffic models.